• We disclose hardware (HW) intrinsic CPU or DSP instructions architecture and microarchitecture that accelerate an approximation of various FP math operations, using standard as well as non-standard floating-point numerics.
  • Our implementation allows configurability of accuracy versus hardware cost at the design time. The accuracy of the functions can be calibrated for various levels of unit of least precision (ULP) target, and/or supporting or elimination for subnormal numbers.
  • It also allows grouping certain operations, such that to minimize HW cost by sharing logic resources across multiple operations.
  • We also disclose CPU arithmetic instructions for handling non-standard floating point numerics.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.