This disclosure describes techniques for fault detection and diagnosis in main and auxiliary (master-slave) systems in a computing device that are coupled via a cable or connector. Per techniques of this disclosure, a multi-level pin is provided on a host System-on-a-Chip (SoC) of the master system that connects to a multi-level voltage generation circuit included in the slave systems. The multi-level voltage generation circuit utilizes a voltage divider that includes multiple parallel resistors and switches to produce a particular voltage level on a pin of cable and/or connector that is indicative of a state of the slave system. The host SoC can verify the state of each voltage regulator and/or connectors just by detecting the voltage level at the multi-level pin. Each particular voltage level is mapped to an operating state of the cable/connector that connects the master system to the slave systems as well as the state of individual voltage regulators on the slave systems.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.