Silicon chip area is expensive, especially for cutting-edge process nodes. Moreover, on-chip wire density has not been scaling well with technology. This disclosure describes techniques that leverage n:1 serdes designs, e.g., double data rate (DDR) design, to reduce wire count and congestion, thus freeing up scarce silicon area. For example, if n=2 (double data rate), wire count and congestion can be reduced by half.

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Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.