Some application-specific integrated circuits (ASICs) do not have counters for forward error correction (FEC) symbol errors so it is not possible to predict a post-FEC bit error rate (BER) when a pre-FEC BER is small (e.g., less than 1E-5). Without FEC statistics, it is not possible to predict a post-FEC BER. To address such a challenge, techniques are presented herein that support a method for predicting post-FEC performance without requiring counters for FEC symbol errors. Aspects of the presented techniques implement a mathematical model which calculates and predicts a post-FEC BER for a given pre-FEC BER. Such a predicted post-FEC BER may subsequently be utilized to develop a frame loss ratio (FLR) and a codewords error ratio (CER).

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.