Sangmoo ChoiFollow


This publication describes systems and techniques directed at block sequential clock driving to minimize dynamic power consumption associated with driving display panels. In an aspect, clock trace structures within display panels configured to minimize parasitic capacitance associated with display panel circuitry are described herein. In further aspects, techniques enabling resistor-capacitor load matching to minimize a perceived, on-screen luminance delta are also described herein. Through such systems and techniques, display panels can reduce power consumption without degrading user experience.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.