Computing Optimal LDPC Decoding Voltages for Flash Memory

Inventor(s)

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Abstract

As flash memory cells age, the boundaries between cell voltages corresponding to ‘1’ and ‘0’ change. Measuring the movement with time of the voltage boundaries (or thresholds, V_TH), and the confidence in the location of the boundaries (log-likelihood ratios, LLR) is critical to the reliable performance of the memory. This disclosure describes techniques for experimentally determining voltage thresholds and log-likelihood ratios values in flash memories, such that optimal V_TH and LLRs can be re-computed periodically or at predetermined ages. Once re-computed, the program-erase (P/E) cycle-optimized values can be used for reading and for soft decoding until the next re-computation of V_TH and LLR. The techniques can enable flash memories to have a longer effective lifespan and reliability.

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Recommended Citation

n/a, "Computing Optimal LDPC Decoding Voltages for Flash Memory", Technical Disclosure Commons, (December 07, 2021)
https://www.tdcommons.org/dpubs_series/4775