Abstract
Currently, the EC, SIO, CPLD, dGPU, thunderbolt and peripheral on‐board devices require to
have external ROM to config their FW setting but each ROM is independent to the others
and doesn’t reserve an enough memory space for patch‐code long service.
Creative Commons License
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Recommended Citation
INC, HP, "A NEW MECHANISM FOR ON-BOARD ROM TO PARALLEL MEMORY ACCESS ARCHITECTURE", Technical Disclosure Commons, (June 25, 2021)
https://www.tdcommons.org/dpubs_series/4417
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