Abstract
This disclosure describes high bandwidth memory (HBM) systems and their assembly. Per techniques of this disclosure, an interposer is utilized to house the HBM module(s) and a chiplet that includes I/O components, e.g., HBM PHY, attached under the HBM die rather than be placed on the main logic die. The chiplet includes an HBM controller, HBM PHY, Die to Die (D2D) connector, tree pattern generator (TGEN), etc., and is utilized to provide I/O connections to the HBM module, which is assembled on an interposer along with the chiplet. An ASIC (or other processor) is connected to the HBM system via a common or separate interposer. The packaging of the ASIC with the HBM system is performed subsequent to quality testing and/or screening of the HBM system.
Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 License.
Recommended Citation
N/A, "High Bandwidth Memory (HBM) System Assembly", Technical Disclosure Commons, (May 25, 2021)
https://www.tdcommons.org/dpubs_series/4331