ASIC power requirements have gone up exponentially due to the demand from IoT computing, AI and big data. The VRM (Voltage regulator module) needs to have high power capabilities and efficiency in order to satisfy the TDP (Thermal Design Power) requirement. High peak power operation mode, has also become an industry practice to improve the ASIC instantaneous throughput. This requires more phase count to support the peak current needed during transient. ASIC chips have also increased in size due to the higher pin count for HSIO (High Speed I/O) and interconnects. In order to fit within the limited VRM placement area, a higher power density VRM design is required.

In order to minimize the VRM solution size, and keep good thermal performances, a stacked inductor with a thermal band wrapped around to make contact with the Power Stage (Driver MOS) underneath is introduced. This solves both the space issue and thermal problems from a conventional stacked inductor design. The thermal band, can be either assembled during the inductor manufacturing stage, or can be clipped on to a regular inductor before the SMT stage. This provides a cost effective, reliable and compact VRM structure. Simulation and test results are verified the effectiveness of the proposed structure.

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