The move from planar to FinFET technology is expected to continue in the future. Current options include Nanosheet, Forksheet and Vertical FET architectures. While vertical FET is attractive, the footprint is currently too large. Improvement of the footprint of vertical FETs can be achieved if the vertical transistors can be stacked on top of each other with an easy integration path.

The present disclosure relates to an integration solution allowing two vertical FET transistors to be stacked on top of each other using a monolithic process integration flow.

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