Logic Forksheet is considered to be the evolution of FinFET technology after nanosheet architecture. The Forksheet architecture uses a forksheet gate that crosses multiple stacked nanosheets. Source/drain epitaxy is usually grown next to the gates requiring gate spacer formation, which causes potentially high parasitic capacitance between gate and source/drain. One approach is to move source/drain epitaxy also in a forksheet geometry on the opposite side of the gate to avoid spacer formation and reduce parasitic capacitance. This approach, however, is not scalable with a classical design due to an isotropic etch process in the process flow. The solution proposed below allows scaling down using double Forksheet architecture to less than the 3nm node using a zigzag shape during fin patterning.

Creative Commons License

Creative Commons License
This work is licensed under a Creative Commons Attribution-Noncommercial-No Derivative Works 4.0 License.