This disclosure describes techniques for the mitigation of voltage droop in computer processor systems. Per techniques of this disclosure, high-density capacitor (cap) modules with plated through holes (PTH) are integrated into an electronic package and/or a printed circuit board (PCB). The pitch and sizing of the PTH and pads are designed to match external connections. Power to devices is delivered vertically through the capacitance module(s) via the PTHs, without any lateral power distribution, thereby reducing voltage droops within the PDN. The capacitor module is placed directly underneath the point of electrical load, with the PTHs aligned with external connections. Electrical connections are provided at the top and bottom sides of the capacitor module. The capacitor module(s) can be integrated into any thick-core organic substrate packaging and/or a PCB that is more than a few layers thick to significantly increase an equivalent capacitance.
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N/A, "Voltage Droop Mitigation Using Integrated High Density Capacitor Modules", Technical Disclosure Commons, (October 29, 2020)