A multi-layer PCB comprises one or more layers made of conducting shapes sandwiched between dielectric layers. The spacing between conducting shapes on a layer is constrained to optimize signal integrity and minimize cross-talk. Such spacing constraints are typically manually calculated and entered into a design tool that enforces the constraints during the design process. Spacing constraints depend on a variety of parameters, including dielectric thicknesses, type of conducting shapes, signal technology, voltage, waveform type, data rate, etc. Manually calculating and maintaining the spacing constraint set across a multi-dimensional matrix of possible values is onerous and error-prone. Engineers frequently simplify the design process by assuming worst-case spacing constraints; the result is a sub-optimally dense PCB. This disclosure describes techniques to automatically calculate spacing constraints given the dielectric thicknesses, conducting shape-pairs, and other parameters. The techniques enable design of efficient, high-density PCBs with excellent signal integrity.

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This work is licensed under a Creative Commons Attribution 4.0 License.